1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device for adjusting a reference voltage for a read from a ferro-electric memory.
2. Description of the Related Art
In recent years, ferro-electric memories (FeRAM) using ferro-electric capacitors have been gathering much attention as nonvolatile semiconductor memories.
FIG. 11 is a circuit diagram schematically showing a cell section of a ferro-electric memory according to the prior art. As shown in this figure, memory that consists of series connected memory cells each having a transistor having a source terminal and a drain terminal and a ferro-electric capacitor inbetween said two terminals, hereafter named “Series connected TC unit type ferro-electric RAM”
Description will be given below of problems with the prior art by referring to a series connected TC unit type ferro-electric RAM by way of example.
A layout pattern of the series connected TC unit type ferro-electric RAM has two types of cells, as shown in FIG. 2: (a) cells having an upper electrode connected to a bit line BL (hereinafter referred to as cells A) and (b) cells having a lower electrode connected to the bit line BL (hereinafter referred to as cells B).
Owing to a difference in interfacial state between the upper electrode and the lower electrode, the polarization characteristic of a ferro-electric capacitor may vary depending on the direction of applied electric fields. This phenomenon is observed as, for example, the lateral asymmetry of a hysteresis loop.
For example, the cell A exhibits a laterally asymmetrical hysteresis curve such as the one shown in FIG. 12. The cell B exhibits a laterally asymmetrical hysteresis curve such as the one shown in FIG. 12. In FIGS. 12 and 13, lines L1 and L2 indicate the characteristics of a bit line capacity Cb. The inclinations of the lines L1 and L2 decrease consistently with the value of the bit line capacity Cb.
If the hysteresis loop is laterally asymmetric, the cells A and B may differ from each other in the absolute value of the amount of signals through the bit line BL.
As shown in FIGS. 14 and 15, the distribution of the signal amount in each cell type, that is, either the cell A or B, exhibits a sufficient signal amount margin between “1” data and “0” data. However, as shown in FIG. 16, the total signal distribution of a combination of the cells A and B exhibits an almost zero signal amount margin between the “1” data and the “0” data.
Prior art document information relating to the invention of the preset application is Jpn. Pat. Appln. KOKAI Publication No. 2003-7095.
As described above, for example, the series connected TC unit type ferro-electric RAM has two types of signal distributions corresponding to the cells A and B. If the signal amount distributions are classified into a plurality of groups and even if each group has a sufficient signal amount margin, these groups as a whole have a smaller signal amount margin. In the worst case, they have a zero margin. Such a reduced margin may result in bad bits. This hinders reliability and yield from being improved.